BRAHMS implements SystemML Links in the form of "manifolds". A manifold is a transport device with one inlet and many outlets, with each outlet attached to the inlet with an integral lag (which may be zero). The manifold as a whole has an associated lag, which is equal to the longest lag of each represented Link (inlet-outlet association).

Pushing data into the inlet is achieved by locking the inlet (permission to write) and then releasing the inlet (write complete). Pulling data out of an outlet is achieved, similarly, by locking the outlet (permission to read) and then releasing the outlet (read complete). Internally, the manifold maintains a single FIFO ring buffer which is written by the inlet and read by the outlets (at different points, depending on their individual lag).

The ring buffer generally has N individual buffers, where N is the manifold lag plus one. However, if the manifold lag is zero, two buffers are still maintained to allow asynchronous operation. In general, extra buffers could be added (as in the zero-lag case) to allow the writer to produce data that the readers are not yet ready to consume, but this will only increase performance under particular circumstances, and has not yet been implemented.

Synchronisation is achieved by a pair of signals associated with each outlet-buffer combination, READ_READY and WRITE_READY. That is, for a manifold with a lag of 2, with 4 outlets connected, there will be 3 buffers and 12 signal pairs in total. Writes are held until all outlets signal WRITE_READY (read complete) on a given buffer, and they cause READ_READY to be signalled on all outlets attached to that buffer. Reads are held until the individual outlet has READ_READY on the given buffer, and they cause a single WRITE_READY signal to be set when complete. This arrangement is effective for any lag.